1. Field of the Invention
The present invention relates to a gate array type integrated circuit structures, and more particularly, relates to a gate array type integrated circuit structure having a novel layout configuration that optimizes manufacturing flexibility.
2. Related Technology
Many conventional integrated circuit structures are formed from repetitive arrays of logic gates. Such integrated circuits are frequently made on substrates of silicon or other semiconductor material, which is processed in the form of a thin wafer having one or more separate integrated circuit devices or die areas on its surface. Conventional integrated circuits or dies typically include many thousands of individual transistors, diodes, and other circuit elements. After the formation of these circuits is completed in each of the die areas, the wafer is then scribed or cut between the dies to physically separate these dies for subsequently packaging and use. The packaging structure usually provides electrical connections from the small-scale circuits on the die to electrical circuitry outside of the package, as well as physical and environmental protection to the packaged circuit die.
Conventionally, integrated circuits are commonly made using a topology or layout which in plan view is bounded on all sides. A conventional integrated circuit structure is presented at FIG. 1 of the appended drawings. Within the die area, the outer periphery of the circuit is defined by an open-centered and rectangular or square array of electrical contact pads. These electrical contact pads are arranged in four intersecting lines that bound the square or rectangular inner area of the semiconductor die. Within this perimeter of electrical contact pads is next arranged an open-centered area of input/output (I/O) devices, which may include power distribution, ground, and data transmission busses, as well as ancillary devices, such as electrostatic discharge protection features. The open-centered array of I/O devices is nested within the array of electrical contact pads, and is connected to the electrical contact pads by conductive traces on the die. These conductive traces may either be formed on a surface of the semiconductor material, and later overlaid with other material or features, or may be alternatively on the finished exterior surface of the die. The resulting integrated circuit structure thus has a first outer and open-centered perimeter area of electrical contact pads surrounding a second inner and open-centered perimeter area of I/O devices.
Within this double perimeter of electrical contact pads and I/O devices, the conventional integrated circuit layout includes a central area of logic gates that are in some applications laid out in an array type configuration. This central area is sometimes referred to as a "sea of gates", and is a form of bounded field within which the logic gates of the integrated circuit are located. These logic gates may number in the tens of thousands or hundreds of thousands in order to accomplish the information processing function for which various application specific circuits may be intended. However, the size of the logic gate array is always circumscribed by the surrounding "walls" of electrical contact pads and I/O devices in the conventional topology of an integrated circuit. This conventional layout for integrated circuit structures is commonly referred to as a "frame" type layout. The perimeter boundary of the circuit is normally termed a "scribe street". The scribing or cutting operation which separates the portions of an integrated circuit processing wafer into individual dies is conducted within these scribe streets.
The number of logic gates in a conventional integrated circuit layout is generally fixed by the available area within the surrounding perimeters of electrical contact pads and I/O devices. Consequently, conventional gate array type integrated circuit devices are normally made in graduated sizes, each size having progressively larger interior areas for the gate arrays. Conventionally, an integrated circuit may have an array of 80,000 logic gates, for example, while the next larger size of logic gate array circuit may have 100,000 gates. When a new application specific integrated circuit design is desired that requires a logic gate array of 85,000 gates, for example, the smaller 80,000 circuit structure is inadequate, while the next larger 100,000 circuit structure is clearly oversized and much more expensive than required to do the intended job.
Much of the cost of integrated circuits is often greatly influenced by the size of the circuit chip, the number of contacts used on the circuit chip, and the size and complexity of the packaging structure used to prepare the integrated circuit chip for its actual use in a circuit. Consequently, the relationship between these factors and the cost of a finished integrated circuit in its package ready for use in an application, such as installation on a circuit board for a computer or other product, is not a linear relationship. In fact, the die size to cost relationship is generally a geometric relationship, and includes recognition that, with increased die size, the yield of good circuit chips from the manufacturing process goes down at a rate that is an exponential of die size.
As a result, the use of an integrated circuit with an array of 100,000 gates for an application specific integrated circuit design requiring merely 85,000 logic gates increases the cost to the consumer considerably above that which would result if a logic gate array of only the desired size were available. On the other hand, the number of logic gate circuits sometimes required for various circuit designs typically does not justify the cost and delay of designing a custom integrated circuit having just a sufficient number of logic gates for the specific application at hand.